View LTC1419ACG_1252806.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1419 14-bit, 800ksps sampling a/d converter with shutdown s f ea t u re n sample rate: 800ksps n power dissipation: 150mw n 81.5db s/(n + d) and 93db thd n no missing codes n no pipeline delay n nap and sleep shutdown modes n operates with 2.5v internal 15ppm/ c reference or external reference n true differential inputs reject common mode noise n 20mhz full-power bandwidth sampling n bipolar input range: 2.5v n 28-pin ssop and so packages d u escriptio the ltc ? 1419 is a 1 m s, 800ksps, 14-bit sampling a/d converter that draws only 150mw from 5v supplies. this easy-to-use device includes a high dynamic range sample-and-hold and a precision reference. two digitally selectable power shutdown modes provide flexibility for low power systems. the ltc1419 has a full-scale input range of 2.5v. out- standing ac performance includes 81.5db s/(n + d) and 93db thd with a 100khz input; 80db s/(n + d) and 86db thd at the nyquist input frequency of 400khz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a m p compatible, 14-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and data ready signal (busy) ease connections to fifos, dsps and microprocessors. u s a o pp l ic at i n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems , ltc and lt are registered trademarks of linear technology corporation. u a o pp l ic at i ty p i ca l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d13(msb) d12 d11 d10 d9 d8 d7 d6 dgnd av dd dv dd v ss busy cs convst rd shdn d0 d1 d2 d3 d4 d5 ltc1419 10 m f 1 m f differential analog input (?.5v to 2.5v) 10 m f 10 m f ?v 5v 14-bit parallel bus m p control lines 1419 ta01 v ref output 2.50v 800khz, 14-bit sampling a/d converter input frequency (hz) effective bits s/(n + d) (db) 10k 100k 1m 2m 1419 ta02 1k 14 13 12 11 10 9 8 7 6 5 4 3 2 86 80 74 68 62 f sample = 800khz effective bits and signal-to-(noise + distortion) vs input frequency
2 ltc1419 av dd = v dd = dv dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss )................................ C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) ......................................... (v ss C 0.3v) to (v dd + 0.3v) digital input voltage (note 4) ......... (v ss C 0.3v) to 10v digital output voltage ........ (v ss C 0.3v) to (v dd + 0.3v) power dissipation ............................................. 500mw operating temperature range ltc1419c............................................... 0 c to 70 c ltc1419i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number cc hara terist ics co u verter with internal reference (notes 5, 6) consult factory for military grade parts. t jmax = 110 c, q ja = 95 c/w (g) t jmax = 110 c, q ja = 130 c/w (sw) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d13(msb) d12 d11 d10 d9 d8 d7 d6 dgnd av dd dv dd v ss busy cs convst rd shdn d0 d1 d2 d3 d4 d5 sw package 28-lead plastic so wide g package 28-lead plastic ssop top view LTC1419ACG ltc1419acsw ltc1419aig ltc1419aisw ltc1419cg ltc1419csw ltc1419ig ltc1419isw ltc1419 ltc1419a parameter conditions min typ max min typ max units resolution (no missing codes) l 13 14 bits integral linearity error (note 7) l 0.8 2 0.6 1.25 lsb differential linearity error l 0.7 1.5 0.5 1 lsb offset error (note 8) l 5 20 5 20 lsb full-scale error internal reference 10 60 10 60 lsb external reference = 2.5v 5 5 lsb full-scale tempco i out(ref) = 0 15 15 ppm/ c symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v, C5.25 v ss C 4.75v l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 15 pf during conversions 5 pf t acq sample-and-hold acquisition time l 90 300 ns t ap sample-and-hold aperture delay time C1.5 ns t jitter sample-and-hold aperture delay time jitter 2 ps rms cmrr analog input common mode rejection ratio C 2.5v < (C a in = a in ) < 2.5v 60 db put u i a a u log (note 5)
3 ltc1419 symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) 4.75 5.25 v v ss negative supply voltage (note 10) C 4.75 C 5.25 v i dd positive supply current l 11 20 ma nap mode shdn = 0v, cs = 0v 1.5 ma sleep mode shdn = 0v, cs = 5v 250 m a i ss negative supply current l 19 30 ma nap mode shdn = 0v, cs = 0v 100 m a sleep mode shdn = 0v, cs = 5v 1 m a symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 100khz input signal l 78 81.5 db 390khz input signal 80.0 db thd total harmonic distortion 100khz input signal, first 5 harmonics l C93 C86 db 390khz input signal, first 5 harmonics C 86 db sfdr spurious free dynamic range 100khz input signal l C95 C86 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 86 db full-power bandwidth 20 mhz full-linear bandwidth s/(n + d) 3 77db 1 mhz (note 5) accuracy ic dy u w a parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v, C 5.25 v ss C 4.75v 0.05 lsb/v v ref output resistance C 0.1ma ? i out ? 0.1ma 2 k w refcomp output voltage i out = 0 4.06 v (note 5) i ter al refere ce characteristics u uu digital i puts a d digital outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i o = C 10 m a 4.5 v i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d13 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d13 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma power require e ts w u (note 5) (note 5)
4 ltc1419 note 6: linearity, offset and full-scale specifications apply for a single- ended +a in input with C a in grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling edge of convst starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best performance ensure that convst returns high either within 650ns after the start of the conversion or after busy rises. (note 5) ti i g characteristics w u symbol parameter conditions min typ max units p dis power dissipation l 150 240 mw nap mode shdn = 0v, cs = 0v 7.5 12 mw sleep mode shdn = 0v, cs = 5v 1.2 mw power require e ts w u (note 5) symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 800 khz t conv conversion time l 950 1150 ns t acq acquisition time l 90 300 ns t acq + conv acquisition + conversion time l 1040 1250 ns t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 40 ns t 3 cs to shdn setup time (notes 9, 10) 40 ns t 4 shdn - to convst wake-up time (note 10) 400 ns t 5 convst low time (notes 10, 11) l 40 ns t 6 convst to busy delay c l = 25pf 20 ns l 50 ns t 7 data ready before busy - 20 50 ns l 15 ns t 8 delay between conversions (note 10) l 40 ns t 9 wait time rd after busy - l C5 ns t 10 data access time after rd c l = 25pf 15 25 ns l 35 ns c l = 100pf 20 35 ns l 50 ns t 11 bus relinquish time 10 20 ns 0 c t a 70 c l 25 ns C40 c t a 85 c l 30 ns t 12 rd low time l t 10 ns t 13 convst high time l 40 ns the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 800khz, t r = t f = 5ns unless otherwise specified.
5 ltc1419 typical perfor m a n ce characteristics u w s/(n + d) vs input frequency and amplitude distortion vs input frequency spurious-free dynamic range vs input frequency differential nonlinearity vs output code integral nonlinearity vs output code input common mode rejection vs input frequency input frequency (hz) signal/(noise + distortion) (db) 90 80 70 60 50 40 30 20 10 0 1k 100k 1m 2m 1419 g01 10k v in = 0db v in = 20db v in = 60db input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 110 1419 g03 thd 2nd 3rd 1k 100k 1m 2m 10k signal-to-noise ratio vs input frequency input frequency (hz) signal-to -noise ratio (db) 1k 0 90 80 70 60 50 40 30 20 10 1419 g02 100k 1m 2m 10k intermodulation distortion plot input frequency (hz) 10k spurious-free dynamic range (db) 0 10 20 30 40 50 60 70 80 90 ?00 ?10 100k 1m 2m 1419 g04 frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 100 200 300 400 1419 g05 ?0 0 50 150 250 350 f sample = 800khz f in1 = 95.8984375khz f in2 = 104.1015625khz output code 0 1.0 dnl error (lsbs) 0.5 0 0.5 1.0 4096 8192 1419 g06 12288 16384 power supply feedthrough vs ripple frequency output code 0 1.0 inl error (lsbs) 0.5 0 0.5 1.0 4096 8192 1419 g07 12288 16384 ripple frequency (hz) amplitude of power supply feedthrough (db) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 2m 1419 g08 10k v ss dgnd v dd input frequency (hz) 1 common mode rejection (db) 80 70 60 50 40 30 20 10 0 10 100 1419 g09 1000 10000
6 ltc1419 pi fu ctio s uu u convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): chip select. the input must be low for the adc to recognize convst and rd inputs. cs also sets the shutdown mode when shdn goes low. cs and shdn low select the quick wake-up nap mode. cs high and shdn low select sleep mode. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. data valid on the rising edge of busy. v ss (pin 26): C 5v negative supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. dv dd (pin 27): 5v positive supply. short to pin 28. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. +a in (pin 1): 2.5v positive analog input. Ca in (pin 2): 2.5v negative analog input. v ref (pin 3): 2.5v reference output. bypass to agnd with 1 m f. refcomp (pin 4): 4.06v reference output. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. agnd (pin 5): analog ground. d13 to d6 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground for internal logic. tie to agnd. d5 to d0 (pins 15 to 20): three-state data outputs. shdn (pin 21): power shutdown input. low selects shutdown. shutdown mode selected by cs. cs = 0 for nap mode and cs = 1 for sleep mode. rd (pin 22): read input. this enables the output drivers when cs is low. 14-bit capacitive dac comp ref amp 2.5v ref 2k refcomp (4.06v) c sample c sample ? ? d13 d0 busy control logic cs convst rd shdn internal clock zeroing switches dv dd v ss av dd +a in ? in v ref agnd dgnd 14 1419 bd + successive approximation register output latches fu ctio al block diagra uu w
7 ltc1419 load circuits for access timing load circuits for output float delay test circuits 1k c l c l dbn (a) hi-z to v oh (b) hi-z to v ol dbn 1k 5v 1419 tc01 1k 100pf 100pf dbn (a) v oh to hi-z (b) v ol to hi-z dbn 1k 5v 1419 tc02 applicatio n s i n for m atio n wu u u conversion details the ltc1419 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps (please refer to digital interface section for the data format). conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the + a in and Ca in inputs are con- nected to the sample-and-hold capacitors (c sample ) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 200ns will provide enough time for the sample- and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the + a in and C a in input charges. the sar contents (a 14-bit data word) which represents the difference of + a in and C a in are loaded into the 14-bit output latches. dynamic performance the ltc1419 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for figure 1. simplified block diagram comp +c sample ? dac ? ? d13 d0 zeroing switches hold hold +a in ? in +c dac ? sample 14 1419 f01 + sar output latch +v dac ? dac hold hold sample sample
8 ltc1419 applicatio n s i n for m atio n wu u u frequencies outside the fundamental. figure 2 shows a typical ltc1419 fft plot. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 800khz the ltc1419 maintains near ideal enobs up to the nyquist input frequency of 400khz (refer to figure 3). frequency (khz) 0 amplitude (db) ?0 ?0 ?0 300 1419 f02a ?0 ?00 100 200 400 250 50 150 350 ?20 ?40 0 f sample = 800khz f in = 99.804687khz sfdr = 98db thd = 93.3db figure 2a. ltc1419 nonaveraged, 4096 point fft, input frequency = 100khz frequency (khz) 0 amplitude (db) ?0 ?0 ?0 300 1419 f02b ?0 ?00 100 200 400 250 50 150 350 ?20 ?40 0 f sample = 800khz f in = 375khz sfdr = 88.3db sinad = 80.1 figure 2b. ltc1419 nonaveraged, 4096 point fft, input frequency = 375khz signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical spectral content with a 800khz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 400khz. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++? 20 234 1 222 2 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1419 has good distortion performance up to the nyquist frequency and beyond. input frequency (hz) effective bits s/(n + d) (db) 10k 100k 1m 2m 1419 ta02 1k 14 13 12 11 10 9 8 7 6 5 4 3 2 86 80 74 68 62 f sample = 800khz figure 3. effective bits and signal/(noise + distortion) vs input frequency
9 ltc1419 applicatio n s i n for m atio n wu u u figure 4. distortion vs input frequency intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magni- tude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb log + () = 20 amplitude at (fa + fb) amplitude at fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 77db (12.5 effective bits). the ltc1419 has been designed to optimize input band- width, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1419 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the C a in input is grounded). the + a in and C a in inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1419 inputs can be driven directly. as source impedance in- creases so will acquisition time (see figure 6). for mini- mum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is figure 5. intermodulation distortion plot frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 100 200 300 400 1419 g05 ?0 0 50 150 250 350 f sample = 800khz f in1 = 95.8984375khz f in2 = 104.1015625khz input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 110 1419 g03 thd 2nd 3rd 1k 100k 1m 2m 10k
10 ltc1419 that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). applicatio n s i n for m atio n wu u u lt ? 1220: 30mhz unity-gain bandwidth voltage feedback amplifier. 5v to 15v supplies. excellent dc specifica- tions. lt1223: 100mhz video current feedback amplifier. 5v to 15v supplies, 6ma supply current. low distortion at frequencies above 400khz. low noise. good for ac applications. lt1227: 140mhz video current feedback amplifier. 5v to 15v supplies, 10ma supply current. lowest distor- tion at frequencies above 400khz. low noise. best for ac applications. lt1229/lt1230: dual/quad 100mhz current feedback amplifiers. 2v to 15v supplies, 6ma supply current each amplifier. low noise. good ac specs. lt1360: 50mhz voltage feedback amplifier. 5v to 15v supplies, 3.8ma supply current. good ac and dc specs. lt1363: 70mhz, 1000v/ m s op amps, 6.3ma supply cur- rent. good ac and dc specs. lt1364/lt1365: dual and quad 70mhz, 1000v/ m s op amps. 6.3ma supply current per amplifier. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1419 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 20mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for source resistance (k w ) 0.01 acquisition time ( m s) 1 1419 f06 0.1 0.01 0.1 110 100 10 figure 6. t acq vs source resistance choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 w ) at the closed-loop band- width frequency. for example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 20mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1419 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifi- cations are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1419. more detailed informa- tion is available in the linear technology databooks, the linearview tm cd-rom and on our web site at www.linear- tech. com. figure 7. rc input filter ltc1419 +a in ? in v ref refcomp agnd 1419 f07 1 2 3 4 5 10 m f 1000pf 50 analog input linearview is a trademark of linear technology corporation.
11 ltc1419 many applications. for example, figure 7 shows a 1000pf capacitor from + a in to ground and a 100 w source resistor to limit the input bandwidth to 1.6mhz. the 1000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input range the 2.5v input range of the ltc1419 is optimized for low noise and low distortion. most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the ltc1419 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1419 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3) see figure 8a. a applicatio n s i n for m atio n wu u u 1 2 3 0.1 m f 10 m f analog input 1419 f08b lt1019a-2.5 v out v in 5v +a in ? in v ref ltc1419 agnd refcomp 5 4 + figure 8b. using the lt1019-2.5 as an external reference 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry, see figure 8b. the reference amplifier gains the voltage at the v ref pin by 1.625 to create the required internal reference voltage. this provides buffering be- tween the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin (refcomp, pin 4) must be bypassed with a capacitor to ground. the refer- ence amplifier is stable with capacitors of 1 m f or greater. for the best noise performance a 10 m f ceramic or 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be driven with a dac or other means shown in figure 9. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal ltc1419 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 5ms should be allowed for after a reference adjustment. figure 8a. ltc1419 reference circuit figure 9. driving v ref with a dac ltc1419 +a in analog input 1.25v to 3v differential ? in v ref refcomp agnd 1419 f09 1 2 3 4 5 10 m f ltc1450 1.25v to 3v r2 40k r3 64k reference amp 10 f refcomp agnd v ref r1 2k bandgap reference 3 4 5 2.500v 4.0625v ltc1419 1419 f08a
12 ltc1419 applicatio n s i n for m atio n wu u u differential inputs the ltc1419 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of + a in C (C a in ) independent of the common mode voltage (see figure 11a). the common mode rejection holds up to extremely high frequencies, see figure 10a. the only requirement is that both inputs can not exceed the av dd or av ss power supply voltages. integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common mode voltage. thd will degrade as the inputs approach either power supply rail, from 86db with a common mode of 0v to 76db with a common mode of 2.5v or C 2.5v. figure 10b. selectable 0v to 5v or 2.5v input range differential inputs allow greater flexibility for accepting different input ranges. figure 10b shows a circuit that converts a 0v to 5v analog input signal with only an additional buffer that is not in the signal path. full-scale and offset adjustment figure 11a shows the ideal input/output characteristics for the ltc1419. the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, C fs + 2.5lsb,... fs C 1.5lsb, fs C 0.5lsb). the output is twos complement binary with 1lsb = fs C (C fs)/16384 = 5v/16384 = 305.2 m v. in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset analog input 1419 f11b 1 2 3 r4 100 w r7 50k r3 24k 5v r6 24k r8 50k r5 47k 4 5 0.1 m f 10 m f +a in ? in v ref refcomp agnd ltc1419 + figure 11b. offset and full-scale adjust circuit figure 10a. cmrr vs input frequency figure 11a. ltc1419 transfer characteristics 1419 f11a 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 fs ?1lsb (fs ?1lsb) input voltage [+a in ?(? in )] output code input frequency (hz) 1 common mode rejection (db) 80 70 60 50 40 30 20 10 0 10 100 1419 g09 1000 10000 ltc1419 +a in analog input ? in v ref 0v to 5v refcomp agnd 1419 f10 1 2 3 2.5v 4 5 10 m f +
13 ltc1419 applicatio n s i n for m atio n wu u u applied to the C a in input. for zero offset error apply C 152 m v (i.e., C 0.5lsb) at + a in and adjust the offset at the Ca in input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 2.499544v (fs/2 C 1.5lsbs) is applied to + a in and r2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. board layout and grounding wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1419, a printed circuit board with ground plane is required. layout should ensure that digital and analog signal lines are separated as much as possible. particular care should be taken not to run any digital track alongside an analog signal track or under- neath the adc.the analog input should be screened by agnd. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd), pin 14 and pin 19 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capacitor and the dv dd bypass capacitor should also be connected to this analog ground plane. no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1419 has differential inputs to minimize noise coupling. common mode noise on the + a in and C a in leads will be rejected by the input cmrr. the C a in input can be used as a ground sense for the + a in input; the ltc1419 will hold and convert the difference voltage between + a in and C a in . the leads to + a in (pin 1) and C a in (pin 2) should be kept as short as possible. in applications where this is not possible, the + a in and C a in traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins as shown in the typical application on the fist page of this data sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypass- ing in a small board space. alternatively, 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. the layout demon- strates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. figure 12. power supply grounding practice 1419 f12 +a in agnd refcomp v ss av dd ltc1419 digital system analog input circuitry 5 4 2 26 28 dv dd 27 dgnd 14 1 10 m f ? in 10 m f 10 m f analog ground plane +
14 ltc1419 applicatio n s i n for m atio n wu u u + +v in gnd a + a agnd dgnd v cc v cc v cc v ss jp4 v logic r14 20 w u4 ltc1419 b[00:13] u5 74hc574 u6 74hc574 56 14 hc14 u7f hc14 u7c 98 hc14 u7d j6-13 j6-14 j6-11 j6-12 j6-9 j6-10 j6-7 j6-8 j6-5 j6-6 j6-3 j6-4 j6-1 j6-2 j6-15 j6-16 j6-17 j6-18 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy dgnd dgnd led jp1 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d[00:13] r0 1.2k r1 r2 r3 r4 r5 r6 r8 r7 r9 r10 r11 r12 r13 header 18-pin 11 10 hc14 u7e r21 1k 12 7 13 v logic v cc gnd u7g hc14 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d12 d11 d10 d09 d08 d07 d06 d00 d01 d02 d03 d04 d05 d13 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 0e 0e data ready notes: unless otherwise specified 1. all resistor values in ohms, 1/10w, 5% 2. all capacitor values in f, 25v, 20% and in pf, 50v, 10% v cc v ss clk j7 v in u2 lt1121-5 d15 ss12 r17 10k r18 10k r19 51 w r16 51 w r15 51 w r20 1m u7a v logic jp5c jp5b jp5a cs rd shdn u7b hc14 hc14 c6 1000pf c11 1000pf c7 1000pf c8 1 m f 16v c13 10 m f 16v c9 10 f 16v c15 0.1 f c16 15pf c5 10 f 16v c2 22 f 10v c10 10 f 10v c1 22 f 10v c12 0.1 f c14 0.1 f gnd tabgnd 1 24 3 c4 0.1 m f c3 0.1 m f u3 lt1363 v v+ 2 3 1 23 4 6 7 8 1 4 j3 7v to 15v j4 jp2 j5 jp3 v out v out j2 1 2 3 4 25 24 23 22 21 28 27 26 5 14 6 7 8 9 10 11 12 13 15 16 17 18 19 20 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 b00 b01 b02 b03 b04 b05 b13 b12 b11 b10 b09 b08 b07 b06 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 +a in ? in v ref refcomp busy cs convst rd shdn av dd dv dd v ss agnd dgnd + + v ss j1 ?v to ?5v d14 ss12 ? in in out 21 5 gnd u1 79l05 + dc124 schem figure 13a. suggested evaluation circuit schematic
15 ltc1419 applicatio n s i n for m atio n wu u u figure 13b. suggested evaluation circuit boardcomponent side silkscreen figure 13c. suggested evaluation circuit boardcomponent side layout
16 ltc1419 applicatio n s i n for m atio n wu u u digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a conversion. internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 0.95 m s and a maximum conversion time over the full operating temperature range of 1.15 m s. no external adjustments are required. the guaranteed maximum acquisition time is 300ns. in addition, a throughput time of 1.25 m s and a minimum sampling rate of 800ksps are guaranteed. power shutdown the ltc1419 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap t 3 cs shdn 1419 f14a figure 14a. cs to shdn timing mode reduces the power by 95% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode the reference is shut down and only a small current remains, about 250 m a. wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 10ms with the recommended 10 m f capacitor. shutdown is con- trolled by pin 21 (shdn); the adc is in shutdown when it is low. the shutdown mode is selected with pin 20 (cs); low selects nap. figure 13d. suggested evaluation circuit boardsolder side layout
17 ltc1419 applicatio n s i n for m atio n wu u u in slow memory and rom modes (figures 19 and 20) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results ap- pear on the data outputs; busy goes high, releasing the processor and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion. t 3 shdn convst 1419 f14b figure 14b. shdn to convst wake-up timing timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figures 16 through 20 show several different modes of operation. in modes 1a and 1b (figures 16 and 17) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 18) cs is tied low. the falling edge of the convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. t 1 cs rd 1419 f15 figure 15. cs to convst set-up timing figure 16. mode 1a. convst starts a conversion. data outputs always enabled data n db13 to db0 data (n + 1) db13 to db0 data (n ?1) db13 to db0 convst cs = rd = 0 busy 1419 f16 t 5 t conv t 6 t 8 t 7 data (sample n) (convst = )
18 ltc1419 applicatio n s i n for m atio n wu u u data (n ?1) db13 to db0 convst busy 1419 f17 t conv t 6 t 13 t 7 cs = rd = 0 data n db13 to db0 data (n + 1) db13 to db0 data t 5 t 6 t 6 t 8 figure 17. mode 1b. convst starts a conversion. data outputs always enabled (convst = ) rd = convst cs = 0 busy 1419 f19 t conv (sample n) t 6 data (n ?1) db13 to db0 data data n db13 to db0 data (n + 1) db13 to db0 data n db13 to db0 t 11 t 8 t 10 t 7 figure 19. slow memory mode timing convst cs = 0 busy 1419 f18 t 5 t conv (sample n) t 8 t 13 t 6 t 9 t 12 data n db13 to db0 t 11 t 10 rd data figure 18. mode 2. convst starts a conversion. data is read by rd
19 ltc1419 u s a o pp l ic at i wu u i for atio rd = convst busy cs = 0 1419 f20 t conv (sample n) t 6 data (n ?1) db13 to db0 data data n db13 to db0 t 10 t 11 t 8 figure 20. rom mode timing information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
20 ltc1419 ? linear technology corporation 1997 1419f lt/tp 0797 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. sw package 28-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s28 (wide) 0996 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ note 1 0.697 ?0.712* (17.70 ?18.08) 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 25 26 11 12 22 21 20 19 18 17 16 15 23 24 14 13 27 28 note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** part number description comments ltc1278/79 single supply, 500ksps/600ksps adcs low power, 5v or 5v supply ltc1400 high speed, serial 12-bit adc 400ksps, complete with internal reference, so-8 package ltc1409 low power, 12-bit, 800ksps sampling adc best dynamic performance, f sample 800ksps, 80mw dissipation ltc1410 12-bit, 1.25msps sampling adc with shutdown best dynamic performance, thd = 84db and sinad = 71db at nyquist ltc1415 single 5v, 12-bit 1.25msps adc single supply, 55mw dissipation ltc1605 single 5v, 16-bit 100ksps adc low power, 10v inputs related parts

▲Up To Search▲

Price & Availability of LTC1419ACG

	To Download LTC1419ACG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .